As digital technologies of electronic devices progress, in order to save data, such as images, there are growing needs for an increase in capacity of a nonvolatile resistance variable element, a reduction in electric power required for writing to the nonvolatile resistance variable element, a reduction in time required for writing to and reading out from the nonvolatile resistance variable element, and an increase in life of the nonvolatile resistance variable element. It is said that although there are such needs, there is a limit to miniaturization of an existing flash memory using a floating gate.
As a first prior art which may be able to respond to the above needs, proposed is a nonvolatile resistance variable element using a perovskite material (such as Pr(1-x)CaXMnO3[PCMO], LaSrMnO3[LSMO], or GdBaCoXOY[GBCO]) (Patent Document 1). In accordance with this technology, the nonvolatile resistance variable element stores data corresponding to a resistance value of the nonvolatile resistance variable element which value increases or decreases by application of a predetermined voltage pulse (waveform voltage whose duration time is short) to the perovskite material.
One method for increasing the capacity of a memory array is to stack a plurality of memory arrays. To stack the memory arrays, it is desirable that the memory array be configured to have a cross-point structure. In the memory array having the cross-point structure, it is necessary to prevent cross talk (current leakage) between adjacent memory cells. To prevent the cross talk, it is effective to arrange a diode in series with a memory element in each memory cell. In the case of switching the resistance value by voltage pulses having different polarities from each other, current needs to flow in both directions, so that a bidirectional current limiting element (element, such as a varistor, whose resistance value becomes high when an absolute value of an applied voltage is less than a critical voltage and becomes extremely low when the absolute value of the applied voltage is the critical voltage or more) is required. However, the bidirectional current limiting element is complex in configuration, and even in the case of using the bidirectional current limiting element, designing, for example, the relation between the resistance value of the resistance variable element and the resistance value of the bidirectional current limiting element is difficult.
As a second prior art which realizes switching of the resistance value by the voltage pulses having the same polarity as each other, proposed is a nonvolatile resistance variable element utilizing a feature that the resistance value of a transition metal oxide (NiO, V2O, ZnO, Nb2O5, TiO2, WO3, or CoO) layer changes by application of the voltage pulse to the transition metal oxide layer (see Patent Document 2). In the resistance variable element using the transition metal oxide layer, the configuration of stacking the cross-point type memory arrays using the diodes is realized.
As a third prior art, proposed is a resistance variable element configured such that a material having a perovskite structure is sandwiched between electrodes, and all write voltage pulses have the same polarity as one another (i.e., the resistance variable element is operated by unipolar drive) (Patent Documents 3 and 4).
As a fourth prior art, proposed is a resistance variable element configured such that a material layer having a spinel structure is sandwiched between electrodes, and the polarity of an electrical pulse for obtaining a high resistance and the polarity of an electrical pulse for obtaining a low resistance are different from each other (i.e., the resistance variable element carries out bipolar drive) (Patent Document 5).
Patent Document 1: U.S. Pat. No. 6,204,139
Patent Document 2: Japanese Laid-Open Patent Application Publication 2004-363604
Patent Document 3: Japanese Laid-Open Patent Application Publication 2004-204348
Patent Document 4: Japanese Laid-Open Patent Application Publication 2004-241396
Patent Document 5: Japanese Laid-Open Patent Application Publication 2006-080259